IC Layout Design Neural Semiconductor

  • Analog & Mixed-Signal Layout Design
  • 12+ years Cumulative Design Experience
  • Standard Cell Library Development
  • Floorplanning
  • Power Planning
  • Physical Verification
  • Parasitic Extraction
  • Block Level & Top Cell Design

Key Expertise

  • Memory Blocks – SRAM & DRAM,
  • D-Flipflop
  • LED Driver
  • PLL
  • ADC
  • DAC
  • Sense Amplifier
  • IO PAD
  • ESD
  • BGR
  • Op-Amp
  • Digital Blocks

Physical Verification

  • LVS
  • DRC
  • EDRC
  • DFM

Process Technology

500nm – Less than 20nm

Design Tools

  • Cadence Virtuoso
  • Tanner L-Edit

Physical Verification Tools

  • Cadence Assura
  • Mentor Graphics Calibre