IC Physical Design (PnR) Neural Semiconductor

With proven methodology and expertise in famous EDA tools, such as Cadence, Synopsis, Mentor Graphics etc., Neural Semiconductor is providing the Physical Design Service with the commitment to ensure the turnaround time, quality of the work and flow and transparent communication in every stage.

The members of the Physical Design Team are experienced in numerous successful tape outs in several process nodes, and also are experienced in developing flows to automate the process to generate the GDS from Gate level Netlist.

Core Responsibilities

  • RTL Synthesis
  • Floorplanning
  • Partitioning
  • Power Planning
  • Placement
  • Clock Tree Synthesis
  • Routing
  • Parasitic Extraction
  • Timing Closure and SI analysis
  • IR and EM analysis
  • Logical Equivalence Check
  • Physical Verification (LVS, DRC, DFM)

Process Technology Exposure

180nm – Less than 20nm