http://neural-semiconductor.com/wp-content/uploads/2018/12/neural-semiconductor-logo-300x94.png 0 0 Quazi Md Mohebur Rahman http://neural-semiconductor.com/wp-content/uploads/2018/12/neural-semiconductor-logo-300x94.png Quazi Md Mohebur Rahman2021-02-11 15:56:172021-02-11 15:56:17ASSOCIATE ENGINEER (TRAINEE) – DIGITAL DESIGN
- RTL design from taking product specification to defining micro-architecture, block specification, and developing IPs.
- Hands-on work and drive various phases of RTL to GDSII flow including synthesis, logic equivalency, and timing constraint development.
- Interact with Place and Route, Static Timing Analysis to drive best implementation for floor planning, clock tree design, timing closure, and low power.
- Work with verification for coverage improvement and debug any issue in the given designs.
- Knowledge on different digital IPs or blocks is appreciable.
Qualification & Competencies:
- B.Sc. in EEE or CSE.
- Prior experience in digital design, verification and all major steps in RTL to GDSII flow is preferred.
- Good command in scripting languages, e.g., Tcl and Python.
- Strong communication skill and a team player.
- Must have ethical values like treating people with respect, professional commitments, inspiring the trust of others and work integrity.
- Commitment to our core values of Leadership, Innovation, Communication, Persistence, Enthusiasm, and Respect.
Application Process: Please submit your resume to email@example.com