Associate Engineer

Digital Verification: 

Senior Engineer – DV: 

Responsibility:

• Functional verification with industry-standard methodologies.
• Working with the RTL team to understand specs and create a verification test plan.

• Creating a SystemVerilog Layered approach or UVM/OVM based Testbenches.
• Understanding problem statements, innovate solutions and implement.
• Be responsible for the assigned tasks from specification to final delivery for subsystem
• and/or SOC.
• Be able to work with a diversified team, proper documentation, and write whitepapers

Qualification & Competencies:

• B.Sc./M.Sc. in EEE or CSE.
• Hands-on experience with the following programming languages: (Verilog, C, C++,
• TCL, Python, etc.) and shell scripting (e.g., Bash) is a plus.
• Fundamentals on timing simulation and Verilog constructs are a must.

• Experienced in writing testcases, Verilog/SystemVerilog-based testbench development, simulation in EDA tools, and debugging.
• Fundamental knowledge about industry-standard protocols (I2C, APB, AHB, AXI, PCIE, etc.) and Verification methodologies.
• Experience in UVM methodology and processor verification.
• Having experience with Assertion based Verification and coverage (Code & Functional) analysis is a plus