Analog Design

Neural Semiconductor Analog Team is composed of a group of highly talented individuals with a diversified skillset and full end to end Analog-Mixed Signal Design expertise. From literature & competitor survey, determination of the best architecture to obtain the most competitive specifications in a given technology, through schematic design, physical implementation & validation, all the way to post silicon correlation. We have an automation team that continuously looks for and implements scripts and flows that expedite repetitive work which translates to rapid time-to-market for our customers.

The team has experience in developing designs & applications using the latest state-of-the-art technology libraries from the world leading semiconductor giants.

Core Competencies

  • Analog Circuit Design & Simulation
  • Analog Layout Design & Simulation
  • Physical Verification
  • EDA Flow Process & Flow Automation
  • Post Silicon Validation

Key Success

3.2GHz, 2GHz, 250MHz Integer N PLL
Selectable 3.21-3.29 GHz Fractional N PLL with 10MHz steps featuring digital sigma delta modulator
12 bit ADC supporting scalable multiple channels for low power applications
300uV resolution comparator featuring auto zero offset cancellation capable of operating up to 100MHz
57dB, 280MHz unity gain bandwidth operational amplifier

Tool Expertise

  • Circuit Design: Virtuoso Schematic Editor
  • Simulation: HSpice, Spectre
  • Layout Design: Virtuoso Layout Editor
  • Verification Tool: PVS, Calibre
  • Parasitic extraction: StarRC , QRC
  • EMIR: Voltus
  • Monte Carlo : Solido, ADE XL
  • Sigma-Delta : Solido, ADE XL
  • Technology: 12nm, 22nm, 28nm, 30nm,
  • Process: FinFET, FDSOI, BICMOS
  • Automation: SKILL, OCEAN and Python

Analog Process Automation

The analog-mixed signal design flow offers several opportunities where automation can be used to reduce human effort, increase productivity as well as improve quality of results. We have a continuously expanding repertoire of scripts developed with SKILL, OCEAN & Python that gives us a competitive edge in time to market. Key automation tasks include:

  • Automated extraction and PEX Simulation of performance monitors using SKILL and Python
  • Generating performance metrics for DFF characterization
  • Generating testbenches to validate if design meets specifications in pre and post layout simulations.
  • Running simulation in both GUI & batch mode and compiling the measurements in any format
  • Running all PV checks for multiple cells simultaneously from a single interface.
  • Automated export of DSPF from CDL & GDS for different configurations of temperature, corner and parasitics.
  • Creating design summary along with detailed reports
  • Checking pin consistency as part of QA
  • Comparing different files such as CDL vs LIB, Verilog vs LIB, LEF vs LIB and Verilog vs LEF as QA to ensure that these are consistent within a given design kit.

Execution Process

  • We work closely with our customers to understand their target market, the specifications we need to achieve, the technology the application is targeting and how it compares to existing designs already available. We go through an extensive literature survey to determine the most suitable architecture to deliver the best PPA.
  • Resource allocation, tape out deadline, complexity of the project, potential risks & its' mitigation are all considered in our planning phase and appropriate decisions are made. The goal is to meet the high expectations of our customers in terms of quality and timely delivery while keeping the impact of unexpected hiccups as small as possible. We are fully transparent in our engagement with our customers ensuring there are no surprises in any stage of the development process.
  • Execution is kicked off as soon as planning is finalized. Circuit designers design and iterate to meet specifications. Once first cut schematics are done, layout designers get to work in physical implementation of the design, optimizing it based on performance requirements. Often schematics are tuned based on feedback from layout designers considering layout dependent effects.
  • We host multiple reviews of the design as it evolves through the flow both internally among the designers as well as with our customers to get feedback and making sure that all things that need to be considered are brought to light and taken care of. Regular physical verification and reliability analysis are performed. We leverage the experience of our customers and consultants to figure out any potential issues that may come up in post silicon that is not visible in post layout simulations. These are accounted for and the design then goes for tapeout.
  • Libraries are cleaned up, final checks are performed and proper signoff documentation are prepared and the gds is ready for submission.
  • We work closely with the Silicon Validation team, both in the design phase & validation phase. In the design phase, we keep testability in mind and design in DFT probes and circuits into the core design itself for debug as well as proper driving circuity to ensure signal integrity along the available testing infrastructure. In the validation phase, we work with the validation team to expedite Silicon bring-up and aid in any necessary debug. Validation plan is well documented which ensures smooth communication with the validation team.

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