Memory Built in Self-Test

The embedded memory requirements of next-generation IoT devices have been increasing rapidly, with demand often growing nearly four times within a period of 2 to 4 years. This trend is largely driven by the need to support advanced wireless protocols and perform localized data processing. Market research highlights that memory components are among the fastest-growing segments within the IoT chip ecosystem in semiconductor industry, currently accounting for approximately 25–30% of the overall semiconductor market.

As a result, the importance of robust memory testing continues to grow. Traditional scan-based testing methods are not suitable for embedded memories, as inserting scan cells for every memory bit is impractical due to significant area, power, and performance overheads. A more effective solution is the use of Memory Built-In Self-Test (MBIST), which offers an efficient and scalable approach to testing embedded memories within these constraints.

MBIST Concept

Memory Built-In Self-Test (MBIST) logic is integrated into a design to apply test patterns to targeted memories, monitor their responses, and verify their ability to accurately store and retrieve data under defined test conditions. This process ensures the proper functionality of memory cells, address decoders, and data paths, helping to detect memory faults such as stuck-at, transition, coupling faults etc. Typically, control signals such as write_enable and chip_select are used to access the memory, as illustrated in the following figure. Within the MBIST architecture, a pattern generator block produces the test data that is written to the memory, while a response checker compares the output data against expected values to determine pass/fail status.

Key Benefits of MBIST

• Improved Test Coverage: MBIST provides comprehensive and high-accuracy testing of embedded memories, often surpassing the capabilities of external test systems.
• Faster Test Execution: By integrating test logic directly within the chip, MBIST accelerates memory testing and shortens overall test cycles.
• Cost Efficiency: On-chip testing reduces dependency on costly external test equipment, lowering overall manufacturing and testing expenses.
• Support for In-Field Diagnostics: MBIST enables post-deployment testing, allowing for real-time fault detection and diagnostics in operational environments.

Pattern Generator

The fundamental aspect of memory testing is the ability to accurately write and read data from the memory. To facilitate this, the MBIST controller includes a pattern generator that produces a sequence of test patterns written into the memory array. These patterns are specifically designed to cover all possible memory cell states, ensuring comprehensive detection of potential faults. The pattern generator creates these sequences based on various memory test algorithms. Memory test algorithms are systematic methods used to generate and apply targeted patterns to memory arrays, aiming to thoroughly stimulate different cell states and transitions to effectively identify faults.

Address Generator

Memory cells are accessed by applying specific addresses to the memory's address pin. To detect various types of memory faults, different testing algorithms are employed, each requiring specific address sequencing patterns. Depending on the algorithm, addresses may need to be incremented row-wise or column-wise. The address generator produces these addresses in accordance with the selected testing algorithm.

Comparator

The comparator is used to evaluate the memory's response by comparing it with the expected data, providing a pass or fail indication based on the result. The comparison is not performed continuously; it occurs only during memory read operations and when a comparison instruction is executed.

MBIST Architecture Planning

Power Domains: Power domain is an important factor when dividing memory across different controllers, but it's not the only one. Designers also consider things like overall power usage, where components are placed on the chip, and how long it takes to test the design. Information about power domains is usually provided using standard formats like UPF (Unified Power Format) or CPF (Common Power Format).

Memory Type Separation: Each memory type (RAM, ROM, DRAM) is assigned to a dedicated controller, with each controller exclusively handling the testing of memories of that specific type.

Clustering by physical region: Memories are grouped based on identical physical region, clock domain, and memory cluster. For multiport memories connected to multiple clock domains, the memory is associated with the clock domain operating at the highest frequency.

Algorithm Consistency: The same algorithm must be applied across all memories under one MBIST controller.

Clocking Architecture

Before inserting MBIST in a design, memory is accessed by functional clocks. As illustrated in the following figure, here, memory is accessed by two functional clocks where fuctional_clk_1 operates at higher frequency than the functional_clk_2.

After inserting MBIST, the clock architecture is configured as illustrated in the following picture. If multiple functional clocks are available in a design, the faster one is used to test the memory.

MBIST Insertion flow

At the initial stage of MBIST insertion, it is essential to define the architecture by determining the number of MBIST controllers to be inserted and assigning each memory to the appropriate controller. The memory test algorithm must be selected based on the overall architecture. Selection criteria include test time, the types of faults detected and the complexity level of the algorithm.

During the design loading phase, HDL files, along with the corresponding library files for both the design and the memories, must be read. The design is then elaborated to prepare it for further processing.

At this stage, it is essential to define the test clocks and various MBIST control signals required for proper operation. Additionally, detailed memory information must be provided, including address partitioning and redundancy specifications (such as spare rows and columns), to ensure accurate configuration and integration of the MBIST logic.

A configuration (or specification) file needs to be prepared to instruct the EDA tool on how to implement the MBIST hardware architecture. This file should be developed based on the MBIST architecture planning and must accurately capture all relevant parameters, such as controller configuration, memory groupings, test algorithms, and control signal definitions. For ROM testing, a signature file containing the expected ROM data is required. As ROMs are read-only memory, the test involves reading data from the ROM and comparing it against the signature to verify the read data.

After implementing the MBIST hardware in the design, test patterns must be generated based on the configured memory test algorithms. These patterns should then be verified through simulation to ensure correct functionality and proper integration of the MBIST logic within the design.

Future Scopes

Modern chip designs present increasing challenges in managing memory test infrastructure, particularly for optimizing MBIST. To address these challenges, we can break the problem into four core areas, each uniquely suited to a different AI methodology. This structured approach allows for faster, more efficient, and higher-quality outcomes compared to traditional, manual techniques.

1. Smart Memory Grouping
2. Optimal Placement for MBIST controllers
3. Power-Aware Scheduling with Genetic Algorithms
4. Fast, Pre-Synthesis Area Estimation via Machine Learning

In future, design architects will specify high-level goals (e.g., test time or power limits), and AI systems will automatically create optimized MBIST solutions that meet those goals, complete with all implementation details.